IC manufacturing typically involves the sequential formation of multiple layers to construct a single integrated device. The materials for each layer are chosen either because their properties allow them to inherently meet the performance criteria for the IC device, or because their properties can be altered through the manufacturing process so that they meet those criteria. One type of material deposited to form a layer within an IC device is a dielectric.
Dielectric materials are electrical insulators, used to substantially electrically isolate conductive layers or features within the IC. The ratio of the amount of electrostatic energy that can be stored by a capacitor using a given dielectric material, as compared to the same capacitor with a vacuum as its dielectric, is defined as its ‘relative dielectric constant’ and is expressed as that material's ‘k’ value. Low-k dielectric materials may be viewed as those with a dielectric constant (‘k’ value) below that of silicon dioxide (for SiO2, k≈4.0-4.2).
As transistor gate widths have shrunken with each subsequent generation of IC development, reducing interconnect delay has now become important just like reducing transistor switching frequency for boosting IC operating speeds. Two contributors to interconnect delay are the resistance of the metal (traditionally aluminum) used for the circuit lines, and the capacitance of the dielectric (traditionally silicon dioxide; SiO2) used for the interlayer dielectric (ILD) material.
To improve speed within the circuit lines, copper, which has approximately 30% lower electrical resistance than aluminum, has replaced aluminum in many high performance IC devices. However, copper has the lowest resistivity of metals incorporated into IC devices, making reduction of dielectric constant of the ILD material an area of strong interest for realizing further decreases in interconnect delay times.
One approach for producing low-k ILD materials involves making the deposited ILD material porous. Porous ILD materials may have substantially lower k values, however, they also are less dense, have greater exposed surface area, and may possess reduced mechanical strength. As a result, porous ILD materials may be damaged or otherwise adversely affected by subsequent IC device fabrication processing. Types of processing that may result in damage to the ILD include dry processing, such as plasma etch, or wet processing, such as resist clean.
Silicon dioxide is one commonly used ILD material. In one instance, molecular bonds within a deposited material, silicon-oxygen-silicon (Si—O—Si) bonds or silicon-carbon (Si—C) bonds for example, may break during processing and subsequently form silicon-hydrogen (Si—H) bonds or silicon-hydroxy (Si—OH) bonds. Such resulting bonds may be more labile, contributing to poor film stability. They may also be more polarizable, thus increasing the dielectric constant of the film. In such instances, the resulting bonds are detrimental to the stability of the deposited material.
In another instance, ‘dangling’ silicon bonds (silicon radicals possessing unpaired electrons) may remain after the deposition process, or Si—H bonds may be formed during deposition. These dangling or Si—H bonds may subsequently form Si—OH bonds upon oxidation, again leading to some of the problems already mentioned. Additionally, dangling bonds may crosslink, increasing stress within the ILD material and leading to ILD cracking or low cohesive strength within the deposited ILD material.
Currently, reducing the aggressiveness of the wet or dry processes used to produce the deposited material is a method to avoid broken or dangling bonds. While this approach may provide some relief, integrating such an approach into the IC fabrication process poses challenges. Processing such as resist strip involves balancing processing parameters to produce integrated circuit devices meeting stringent and ever increasing performance requirements and tightening dimensional tolerances. Such processing becomes more difficult to accomplish successfully when critical process parameters are altered for the purpose of preventing broken or dangling bonds.
The presence of broken, detrimental or dangling bonds (collectively referred to hereinafter as ‘detrimental bonds’) in deposited ILD materials is an impediment to successful IC fabrication and to the optimal and reliable performance of IC devices incorporating such materials. Other types of deposited materials may likewise be affected by the presence of detrimental bonds during or after processing.